An SRAM (Static Random Access Memory) has been well known as a volatile memory circuit used for an electronic apparatus. FIG. 1 is a circuit diagram illustrating a memory cell of an SRAM using MOS (Metal Oxide Semiconductor) Field Effect Transistor (FET). The memory cell has a bistable circuit 30, two input/output transistors m5 and m6. A CMOS inverter 10 (a first inverter circuit) and a CMOS inverter 20 (a second inverter circuit) are coupled in a ring shape in the bistable circuit 30. The inverter 10 includes a p-type MOSFET m1 and an n-type MOSFET m2. In the FET m1 and the FET m2, sources are coupled to a power source Vsupply and a ground respectively, gates are commonly-coupled to a node Q, and drains are commonly coupled to a node QB. The inverter 20 includes a p-type MOSFET m3 and an n-type MOSFET m4. In the FET m3 and the FET m4, sources are coupled to a power source Vsupply and a ground respectively, gates are commonly-coupled to the node QB, and drains are commonly-coupled to the node Q. As described above, the inverter 10 is coupled to the inverter 20 in a ring shape. The node Q is coupled to a data input/output line DIN via an n-type FET m5, and the node QB is coupled to a data input/output line DINB via an n-type FET m6. Gates of FETs m5 and m6 are coupled to a word line WL.
According to above composition, it is possible to write and hold data in the bistable circuit 30, and read data from the bistable circuit 30. However, an SRAM consumes power while holding data. In addition, when the power source is shut down, data stored in the bistable circuit 30 is lost. Since the bistable circuit 30 has a symmetrical structure, and symmetrically-operates, once nodes Q and QB have the same potential after the power source is shut down, it is impossible to restore data even though the power source is restored. This is because potentials of nodes Q and QB remain at the same potential and data is determined by external noise and the like at certain timing regardless of the data stored before the power source is shut down when the power source is restored.
A volatile latch circuit used for an electronic apparatus is well known. FIG. 2 is a circuit diagram illustrating a D latch circuit using a MOS (Metal Oxide Semiconductor) Field Effect Transistor (FET) as an example of a latch circuit. The D latch circuit includes the bistable circuit 30, and pass gates 80 and 90. The CMOS inverter 10 (the first inverter circuit) and the CMOS inverter 20 (the second inverter circuit) are coupled to the bistable circuit 30 via the pass gate 90 in a ring shape. The inverter 10 includes the p-type MOSFET m1 and the n-type MOSFET m2. In the FET m1 and FET m2, sources are coupled to the power source Vsupply and ground respectively, gates are commonly-coupled to the node Q, and drains are commonly-coupled to the node QB. The inverter 20 includes the p-type MOSFET m3 and the n-type MOSFET m4. In the FET m3 and the FET m4, sources are coupled to the power source Vsupply and a ground respectively, gates are commonly-coupled to the node QB, and drains are commonly-coupled to the node Q via the pass gate 90. As described above, the inverter 10 is coupled to the inverter 20 in a ring shape.
The pass gate 80 (a first input switch) is coupled between the input line DIN and the node Q. The pass gate 80 includes the p-type MOSFET m5 and the n-type MOSFET m6. The source and drain of the FET m5 are coupled to the source and drain of the FET m6 respectively. An inverted clock signal CLKB is input to the gate of the FET m5, and a clock signal CLK is input to the gate of the FET m6. When the clock signal CLK at a high level is input, both FETs m5 and m6 become conductive, and the pass gate 80 becomes conductive. The pass gate 90 (a second input switch) is coupled between the node Q and the inverter 20. The pass gate 90 includes a p-type MOSFET m7 and an n-type MOSFET m8. The clock signal CLK is input to the gate of the FET m7, and the inverted clock signal CLKB is input to the gate of the FET m8. When the clock signal CLK at a low level is input, both FETs m7 and m8 become conductive, and the pass gate 90 becomes conductive. Other connections and behavior are same as the pass gate 80.
According to above composition, when the clock signal CLK is at a high level, the pass gate 80 becomes conductive, and the pass gate 90 becomes non-conductive. This makes data of the input line DIN written in the bistable circuit 30. When the clock signal CLK is at a low level, the pass gate 80 becomes non-conductive, and the pass gate 90 becomes conductive. This makes the bistable circuit 30 hold data. The data stored in the bistable circuit 30 can be output from the node Q or QB. A volatile D latch circuit consumes power while holding data. In addition, if the power source is shut down, the data stored in the bistable circuit 30 is lost. The bistable circuit 30 does not function as a bistable circuit when the pass gate 90 is non-conductive, but on the other hand, as the pass gate 80 is conductive, the data of the input line DIN is written in the node Q and the logic-inverted data of the node Q is written in the node QB. Therefore, the data of nodes Q and QB are determined regardless of the data stored before the power source is shut down. Since the bistable circuit 30 has a symmetrical structure where inputs and outputs of the inverter 10 and the inverter 20 are coupled each other and symmetrically-operates in a condition that the pass gate 90 is conductive, once nodes Q and QB have the same potential after the power source is shut down, it is impossible to restore the data even though the power source is restored. This is because potentials of nodes Q and QB remain at the same potential and data is determined by external noise and the like at certain timing regardless of the data stored before the power source is shut down when the power source is restored.
A flash memory, an MRAM (Magnetic Random Access Memory), an FeRAM (Ferroelectric Random Access Memory), a PRAM (Phase-change Random Access Memory) and the like are known as a nonvolatile memory circuit where data is not lost even though a power source is shut down. Since data is not lost in these memory circuits even though a power source is shut down, the data can be read out when the power source is restored after that.
Patent Reference 1 discloses an MRAM where ferromagnetic tunnel junction devices are coupled to each of complementary nodes of a latch circuit.    [Patent Reference 1] Japanese Patent Application Publication No. 2006-19008